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Disambiguation of "Rebeiro, Chester"

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GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks.

, , , , and . IEEE Embed. Syst. Lett., 10 (3): 83-86 (2018)

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Alexander Chester

Andrew Chester

Chester Avilés

William Chester Tepper

 

Other publications of authors with the same name

ApproxBC: Blockchain Design Alternatives for Approximation-Tolerant Resource-Constrained Applications., , , , and . IEEE Communications Standards Magazine, 2 (3): 45-51 (2018)XFC: A Framework for eXploitable Fault Characterization in Block Ciphers., , and . DAC, page 8:1-8:6. ACM, (2017)Shakti-T: A RISC-V Processor with Light Weight Security Extensions., , , , and . HASP@ISCA, page 2:1-2:8. ACM, (2017)Boosting Profiled Cache Timing Attacks With A Priori Analysis., and . IEEE Trans. Inf. Forensics Secur., 7 (6): 1900-1905 (2012)PERI: A Posit Enabled RISC-V Core., , , and . CoRR, (2019)Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs., , and . Integr., 45 (3): 307-315 (2012)Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER., , , , and . IEEE Comput. Archit. Lett., 19 (1): 9-12 (2020)High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms., and . INDOCRYPT, volume 5365 of Lecture Notes in Computer Science, page 376-388. Springer, (2008)D-TIME: Distributed Threadless Independent Malware Execution for Runtime Obfuscation., , and . WOOT @ USENIX Security Symposium, USENIX Association, (2019)Pinpointing Cache Timing Attacks on AES., , and . VLSI Design, page 306-311. IEEE Computer Society, (2010)