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Disambiguation of "Flamand, Eric"

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Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.

, , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (10): 2700-2713 (2017)

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Claudiu Melian-Flamand

Ull Erich

Hauke Erichsen

Gerda Erich

Badrian Erich

 

Other publications of authors with the same name

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)PRO3D: programming for future 3D manycore architectures., , , , , , and . INA-OCMC@HiPEAC, page 47-50. ACM, (2012)The transprecision computing paradigm: Concept, design, and applications., , , , , , , , , and . DATE, page 1105-1110. IEEE, (2018)Accelerating RNN-Based Speech Enhancement on a Multi-core MCU with Mixed FP16-INT8 Post-training Quantization., , , , and . PKDD/ECML Workshops (1), volume 1752 of Communications in Computer and Information Science, page 606-617. Springer, (2022)Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs., , , and . AICAS, page 1-4. IEEE, (2021)Strategic directions towards multicore application specific computing.. DATE, page 1266. IEEE, (2009)Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 57 (1): 127-139 (2022)Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters., , , , , and . CoRR, (2023)A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory., , and . CASES, page 6:1-6:10. IEEE, (2013)P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator., , , and . DATE, page 983-987. IEEE, (2012)