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Disambiguation of "Tsai, Chien-Chung"

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Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

, , , , and . ISQED, page 99-104. IEEE Computer Society, (2003)

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Schi-chien Tsai

Chien-Chung Fu

Chien-Chung Huang

Chieh Chien

Rey-Djin Chien

 

Other publications of authors with the same name

Boolean Functions Classification via Fixed Polarity Reed-Muller Forms., and . IEEE Trans. Computers, 46 (2): 173-186 (1997)Synthesis of Scan Chains for Netlist Descriptions at RT-Level., , , , , and . J. Electron. Test., 18 (2): 189-201 (2002)Generalized Reed-Muller Forms as a Tool to Detect Symmetries., and . IEEE Trans. Computers, 45 (1): 33-40 (1996)Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms., and . ISCAS, page 287-290. IEEE, (1994)Multilevel Logic Synthesis for Arithmetic Functions., and . DAC, page 242-247. ACM Press, (1996)Boolean Matching Using Generalized Reed-Muller Forms., and . DAC, page 339-344. ACM Press, (1994)On Concurrent Test of Core-Based SOC Design., , , , , , and . J. Electron. Test., 18 (4-5): 401-414 (2002)Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D., , , , , , and . Asian Test Symposium, page 265-. IEEE Computer Society, (2001)Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm., , , , , , , and . ITC, page 74-82. IEEE Computer Society, (2002)On RTL scan design., , , , , , and . ITC, page 728-737. IEEE Computer Society, (2001)