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Technology Decomposition and Mapping Targeting Low Power Dissipation.

, , and . DAC, page 68-73. ACM Press, (1993)

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Cache design trade-offs for power and performance optimization: a case study., and . ISLPD, page 63-68. ACM, (1995)Design decisions influencing the microarchitecture for a Prolog machine., , and . MICRO, page 217-231. ACM/IEEE, (1984)The Aquarius IIU System., , , , and . ICSI, page 38-46. IEEE Computer Society, (1990)Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations., and . IEEE Trans. Computers, 33 (5): 414-426 (1984)High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers., and . DAC, page 135-140. IEEE Computer Society Press, (1992)Hardware-software co-designing benchmark-driven superpipelined instruction set processors., and . COMPSAC, IEEE, (1994)Low-power state assignment targeting two- and multilevel logic implementations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (12): 1281-1291 (1998)Design and Analysis of Hardware for High-Performance Prolog., , , , and . J. Log. Program., 29 (1-3): 107-139 (1996)Efficient estimation of dynamic power consumption under a real delay model., , and . ICCAD, page 224-228. IEEE Computer Society / ACM, (1993)Low power state assignment targeting two-and multi-level logic implementations., , , and . ICCAD, page 82-87. IEEE Computer Society / ACM, (1994)