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High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (8): 2296-2306 (2017)

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , and . DATE, page 1634-1639. IEEE, (2018)High density emerging resistive memories: What are the limits?, , , , and . LASCAS, page 1-4. IEEE, (2017)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , and . NANOARCH, page 7-12. ACM, (2016)Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , and . DATE, page 298-301. IEEE, (2020)Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices., , , , , , , , , and 2 other author(s). VLSI-SoC, page 180-183. IEEE, (2018)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology., , , , , , , , , and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology., , and . DELTA, page 241-244. IEEE Computer Society, (2010)A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation., , and . ISCAS, page 3022-3025. IEEE, (2007)Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)