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Disambiguation of "Marongiu, Andrea"

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Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine.

, , , and . CoRR, (2018)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Federico Marongiu

Daniele Marongiu

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)
 

Other publications of authors with the same name

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators., , , , , and . IEEE Trans. Computers, 64 (8): 2132-2144 (2015)On the Cost of Freedom From Interference in Heterogeneous SoCs., , and . SCOPES, page 31-34. ACM, (2018)Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution., , , , , and . ACM Great Lakes Symposium on VLSI, page 9-14. ACM, (2015)A tightly-coupled multi-core cluster with shared-memory HW accelerators., , , , , and . ICSAMOS, page 96-103. IEEE, (2012)OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs., , and . SSS, volume 5873 of Lecture Notes in Computer Science, page 547-562. Springer, (2009)A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment., , , and . DSD, page 9-17. IEEE, (2021)Mixed-data-model heterogeneous compilation and OpenMP offloading., , , , , , and . CC, page 119-131. ACM, (2020)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs., , , , , , and . DATE, page 491-496. IEEE, (2012)A Software Stack for Next-Generation Automotive Systems on Many-Core Heterogeneous Platforms., , , , , and . DSD, page 55-59. IEEE Computer Society, (2016)Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology., , , and . DSD, page 259-266. IEEE Computer Society, (2008)