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CheriRTOS: A Capability Model for Embedded Devices., , , , , , , , , and 6 other author(s). ICCD, page 92-99. IEEE Computer Society, (2018)Randomized Testing of RISC-V CPUs Using Direct Instruction Injection., , , , , , , , , and . IEEE Des. Test, 41 (1): 40-49 (February 2024)Cornucopia: Temporal Safety for CHERI Heaps., , , , , , , , , and 14 other author(s). SP, page 608-625. IEEE, (2020)CHERI JNI: Sinking the Java Security Model into the C., , , , , , , , , and 5 other author(s). ASPLOS, page 569-583. ACM, (2017)Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process., , , , , , , , , and 3 other author(s). SP, page 1003-1020. IEEE, (2020)CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment., , , , , , , , , and 11 other author(s). ASPLOS, page 379-393. ACM, (2019)Fast Protection-Domain Crossing in the CHERI Capability-System Architecture., , , , , , , , , and 9 other author(s). IEEE Micro, 36 (5): 38-49 (2016)CHERI Concentrate: Practical Compressed Capabilities., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (10): 1455-1469 (2019)Architectural Contracts for Safe Speculation., , , , , , , , , and 3 other author(s). ICCD, page 578-586. IEEE, (2023)High-performance memory safety: optimizing the CHERI capability machine.. University of Cambridge, UK, (2018)British Library, EThOS.