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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren, N. Waldron, P. Wambacq, N. Collaert, and D. Verkest. ESSDERC, page 158-161. IEEE, (2018)

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Bertrand Hirl

Bertrand Gloddek

Joachim Bertrand

Bertrand Malmendier

Jessica Bertrand

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A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication.V. Vidojkovic, V. Szortyka, K. Khalaf, G. Mangraviti, S. Brebels, W. Thillo, K. Vaesen, B. Parvais, V. Issakov, M. Libois and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS.V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk, and P. Wambacq. IEEE J. Solid State Circuits, 50 (9): 2025-2036 (2015)A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs.R. ElKashlan, H. Yu, A. Khaled, S. Yadav, U. Peralagu, A. Alian, N. Collaert, P. Wambacq, and B. Parvais. ESSDERC, page 152-155. IEEE, (2023)Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures.A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, and I. Radu. IRPS, page 1-6. IEEE, (2020)Back-gate bias effect on UTBB-FDSOI non-linearity performance.B. Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, and J. Raskin. ESSDERC, page 148-151. IEEE, (2017)Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications.D. Yan, M. Ingels, G. Mangraviti, Y. Liu, B. Parvais, N. Waldron, N. Collaert, and P. Wambacq. NEWCAS, page 1-4. IEEE, (2019)A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s.V. Vidojkovic, G. Mangraviti, K. Khalaf, V. Szortyka, K. Vaesen, W. Thillo, B. Parvais, M. Libois, S. Thijs, J. Long and 2 other author(s). ISSCC, page 268-270. IEEE, (2012)Impact of III-N buffer layers on RF losses and harmonic distortion of GaN-on-Si Substrates.P. Cardinael, S. Yadav, M. Zhao, M. Rack, D. Lederer, N. Collaert, B. Parvais, and J. Raskin. ESSDERC, page 303-306. IEEE, (2021)Understanding the memory window in 1T-FeFET memories: a depolarization field perspective.K. Kaczmarek, M. Bardon, Y. Xiang, L. Breuil, N. Ronchi, B. Parvais, G. Groeseneken, and J. Houdt. IMW, page 1-4. IEEE, (2021)CMOS compatible GaN-on-Si HEMT technology for RF applications: analysis of substrate losses and non-linearities.S. Yadav, P. Cardinael, M. Zhao, K. Vondkar, U. Peralagu, A. Alian, A. Khaled, S. Makovejev, E. Ekoga, D. Lederer and 3 other author(s). ICICDT, page 1-4. IEEE, (2021)

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Disambiguation of "Parvais, Bertrand"

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Please choose a person to relate this publication to

Bertrand Hirl

Bertrand Gloddek

Joachim Bertrand

Bertrand Malmendier

Jessica Bertrand

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Parvais, Bertrand"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Please choose a person to relate this publication to

Bertrand Hirl

Bertrand Gloddek

Joachim Bertrand

Bertrand Malmendier

Jessica Bertrand

Other publications of authors with the same name

Disambiguation

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URL
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Chicago
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Scaling CMOS beyond Si FinFET: an analog/RF perspective.