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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren, N. Waldron, P. Wambacq, N. Collaert, and D. Verkest. ESSDERC, page 158-161. IEEE, (2018)

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João Veloso

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.A. Veloso, G. Eneman, A. Keersgieter, P. Favia, A. Hikavyy, R. Chen, A. Jourdain, and N. Horiguchi. ICICDT, page 51-54. IEEE, (2022)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.T. Bao, A. Veloso, S. Sakhare, P. Matagne, J. Ryckaert, M. Perumkunnil, D. Crotti, F. Yasin, A. Spessot, A. Furnémont and 2 other author(s). DAC, page 13. ACM, (2019)Beyond-Si materials and devices for more Moore and more than Moore applications.N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, T. Ivanov, D. Lin, J. Mitard, S. Ramesh and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices.C. Coelho, J. Martino, M. Bellodi, E. Simoen, A. Veloso, and P. Agopian. Microelectron. J., (2021)Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors.A. Rothschild, R. Mitsuhashi, C. Kerner, X. Shi, J. Everaert, L. Date, T. Conard, O. Richard, C. Vrancken, R. Verbeeck and 8 other author(s). Microelectron. Reliab., 47 (4-5): 521-524 (2007)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors.E. Simoen, A. Oliveira, A. Veloso, A. Chasin, R. Ritzenthaler, H. Mertens, N. Horiguchi, and C. Claeys. ASICON, page 1-4. IEEE, (2019)NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase.A. Shickova, B. Kaczer, A. Veloso, M. Aoulaiche, M. Houssa, H. Maes, G. Groeseneken, and J. Kittl. Microelectron. Reliab., 47 (4-5): 505-507 (2007)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.A. Veloso, A. Jourdain, D. Radisic, R. Chen, G. Arutchelvan, B. O'Sullivan, H. Arimura, M. Stucchi, A. Keersgieter, M. Hosseini and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)

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Disambiguation of "Veloso, Anabela"

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Please choose a person to relate this publication to

João Veloso

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Disambiguation of "Veloso, Anabela"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaling CMOS beyond Si FinFET: an analog/RF perspective.

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João Veloso

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Disambiguation

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.