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High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , and . ISLPED, page 79-84. IEEE/ACM, (2011)A morphable phase change memory architecture considering frequent zero values., , , and . ICCD, page 373-380. IEEE Computer Society, (2011)MLC PCM main memory with accelerated read., , , , and . ISPASS, page 143-144. IEEE Computer Society, (2016)Optimizing energy consumption in GPUS through feedback-driven CTA scheduling., , , and . SpringSim (HPC), page 12:1-12:12. ACM, (2017)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs., , , and . IEEE Trans. Computers, 67 (7): 1054-1061 (2018)HL-PCM: MLC PCM Main Memory with Accelerated Read., , , , and . IEEE Trans. Parallel Distributed Syst., 28 (11): 3188-3200 (2017)Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories., , , , , and . DSN, page 85-96. IEEE Computer Society, (2017)