Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 200MSPS time-interleaved 12-bit ADC system with digital calibration., , , , and . MWSCAS, page 1184-1187. IEEE, (2017)A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier., , , , , , , , , and . IEEE Trans. Circuits Syst., 67-I (11): 3618-3629 (2020)Brain Storm Optimization Algorithm with Modified Step-Size and Individual Generation., , and . ICSI (1), volume 7331 of Lecture Notes in Computer Science, page 243-252. Springer, (2012)A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator., , , , , and . IEEE J. Solid State Circuits, 55 (8): 2140-2150 (2020)A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (4): 756-767 (2018)A 13bit 200MS/S pipeline ADC with current-mode MDACs., , , , , and . ISCAS, page 1-4. IEEE, (2017)Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (1): 20-28 (January 2024)A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration., , and . SoCC, page 13-17. IEEE, (2016)A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs., , , , , , , and . IEEE J. Solid State Circuits, 53 (11): 3280-3292 (2018)A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3373-3383 (2019)