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Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores.

, , , and . CoRR, (2019)

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Virtual Simulation of Distributed IP-based Designs., , and . DAC, page 50-55. ACM Press, (1999)Origami: A 803-GOp/s/W Convolutional Network Accelerator., and . IEEE Trans. Circuits Syst. Video Techn., 27 (11): 2461-2475 (2017)Efficient Image Dataset Classification Difficulty Estimation for Predicting Deep-Learning Accuracy., , , , , and . CoRR, (2018)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . CoRR, (2018)CAS-CNN: A deep convolutional neural network for image compression artifact suppression., , and . IJCNN, page 752-759. IEEE, (2017)Design and Analysis of NoCs for Low-Power 2D and 3D SoCs., , , and . Low Power Networks-on-Chip, Springer, (2011)Dynamic thermal clock skew compensation using tunable delay buffers., , , , , , , and . ISLPED, page 162-167. ACM, (2006)Contents provider-assisted dynamic voltage scaling for low energy multimedia applications., , and . ISLPED, page 42-47. ACM, (2002)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , and . CODES+ISSS, page 39-48. ACM, (2011)Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)