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Disambiguation of "Kang, Kunhyuk"

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Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.

, , , and . IET Circuits Devices Syst., 4 (6): 469-478 (2010)

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Mujin Kang

Ewha Kang

Mihyun Kang

Kang Teng

Andree Kang

 

Other publications of authors with the same name

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 270-280 (2010)Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations., , and . ICCAD, page 736-741. IEEE Computer Society, (2005)Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters., , and . ACM Trans. Design Autom. Electr. Syst., 11 (4): 848-879 (2006)Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement., , , , and . DAC, page 358-363. IEEE, (2007)Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 497-502 (2010)Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ., , and . ITC, page 1-10. IEEE Computer Society, (2007)Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 743-751 (2007)Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations., , , , and . ISLPED, page 14-19. ACM, (2005)Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop., , and . DAC, page 934-939. IEEE, (2007)Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI., , , and . ICCD, page 216-221. IEEE, (2006)