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Application-aware spinlock control using a hardware scheduler in MPSoC platforms., , , , , , and . ISSoC, page 1-6. IEEE, (2012)Optimized communication architecture of MPSoCs with a hardware scheduler: A system view., , , , , , and . SoC, page 163-168. IEEE, (2010)Efficient Implementation of Application-Aware Spinlock Control in MPSoCs., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 4 (1): 64-84 (2013)Synthesis of pipelined DSP accelerators with dynamic scheduling., , , and . ISSS, page 72-77. ACM, (1995)Synthesis of pipelined DSP accelerators with dynamic scheduling., , , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (1): 59-68 (1997)A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms., , , , , , and . DATE, page 876-881. IEEE Computer Society, (2005)Task management in MPSoCs: An ASIP approach., , , , , and . ICCAD, page 587-594. ACM, (2009)An Overview of Open SystemC Initiative Standards Development., , , , and . IEEE Des. Test Comput., 29 (2): 14-22 (2012)Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)