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A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.

, , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 13 (2): 31:1-31:21 (2008)

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A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems., , and . IEEE Trans. Computers, 53 (4): 467-482 (2004)State-of-the-Art SoC Communication Architectures., , , and . Embedded Systems Handbook, CRC Press, (2005)Origami: A 803-GOp/s/W Convolutional Network Accelerator., and . IEEE Trans. Circuits Syst. Video Techn., 27 (11): 2461-2475 (2017)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . CoRR, (2018)Virtual Simulation of Distributed IP-based Designs., , and . DAC, page 50-55. ACM Press, (1999)Efficient Image Dataset Classification Difficulty Estimation for Predicting Deep-Learning Accuracy., , , , , and . CoRR, (2018)Design and Analysis of NoCs for Low-Power 2D and 3D SoCs., , , and . Low Power Networks-on-Chip, Springer, (2011)Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms., , and . CASES, page 145-149. ACM, (2007)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , and . CODES+ISSS, page 39-48. ACM, (2011)A Minimally Invasive Low-Power Platform for Real-Time Brain Computer Interaction Based on Canonical Correlation Analysis., , , , and . IEEE Internet of Things Journal, 6 (1): 967-977 (2019)