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The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design.

, and . DAC, page 673-678. IEEE Computer Society Press, (1990)

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CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology., , , and . DAC, page 597-600. ACM, (1988)What we know after twelve years developing and deploying test data analytics solutions., , and . ITC, page 1-8. IEEE, (2016)Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling., , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)Facilitating Rapid First Silicon Debug., , and . ITC, page 628-637. IEEE Computer Society, (2002)Modeling Test Escape Rate as a Function of Multiple Coverages., , and . ITC, page 1-9. IEEE Computer Society, (2008)The roles of controllability and observability in design for test., , , and . VTS, page 211-216. IEEE Computer Society, (1992)Test Generation and Design for Test for a Large Multiprocessing DSP., , , and . ITC, page 149-156. IEEE Computer Society, (1995)Exact ordered binary decision diagram size when representing classes of symmetric functions., , and . J. Electron. Test., 2 (3): 243-259 (1991)Efficient Process Shift Detection and Test Realignment., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (12): 1934-1942 (2013)Multidimensional Test Escape Rate Modeling., , , , and . IEEE Des. Test Comput., 26 (5): 74-82 (2009)