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A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.

T. Lin, C. Chien, P. Chang, C. Chen, P. Wang, T. Shyu, C. Chou, S. Luo, J. Guo, T. Chen, G. Chuang, Y. Chu, L. Cheng, H. Su, C. Jou, M. Ieong, C. Wu, and J. Wang. ISSCC, page 158-159. IEEE, (2013)

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Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Collaborative voltage scaling with online STA and variable-latency datapath.T. Lin, P. Hsiao, C. Lin, S. Kuo, C. Lin, Y. Kuo, C. Liu, and Y. Chu. ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2010)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, and Y. Chu. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.H. Huang, J. Wang, Y. Chu, T. Wu, K. Cheng, and C. Wu. ISCAS, page 1572-1575. IEEE, (1995)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.P. Wu, Y. Kuo, C. Wu, C. Chuang, Y. Chu, and W. Hwang. SoCC, page 136-139. IEEE, (2014)An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation.M. Chen, M. Chang, Y. Chu, and W. Hwang. SoCC, page 5-10. IEEE, (2012)Design of STR level converters for SoCs using the multi-island dual-VDD design technique.J. Wang, Y. Chang, C. Yeh, and Y. Chu. ISCAS, IEEE, (2006)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, and T. Yang. A-SSCC, page 361-364. IEEE, (2014)Energy-efficient RISC design with on-demand circuit-level timing speculation.T. Lin, Y. Kuo, Y. Tsai, T. Shyu, and Y. Chu. ASP-DAC, page 477-478. IEEE, (2012)An ultra-low power interface CMOS IC design for biosensor applications.W. Hu, Y. Liu, V. Das, C. Schecht, T. Nguyen, D. Lie, T. Yan, C. Kuo, S. Wu, Y. Chu and 1 other author(s). MWSCAS, page 1196-1199. IEEE, (2012)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.T. Lin, C. Chien, P. Chang, C. Chen, P. Wang, T. Shyu, C. Chou, S. Luo, J. Guo, T. Chen and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)

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Disambiguation of "Chu, Yuan-Hua"

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A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.

Please choose a person to relate this publication to

Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chu, Yuan-Hua"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.

Please choose a person to relate this publication to

Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.