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A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs., , , and . IEEE Trans. Multi Scale Comput. Syst., 1 (3): 159-167 (2015)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS., , , , , , , , , and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 183-192 (2011)Variation-aware and adaptive-latency accesses for reliable low voltage caches., , , , , , , , and . VLSI-SoC, page 358-363. IEEE, (2013)Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 969-973 (2016)A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 908-912 (2012)Variation-resilient voltage generation for SRAM weak cell testing., , , and . ASICON, page 248-251. IEEE, (2011)Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier., , and . IEICE Trans. Electron., 95-C (1): 172-175 (2012)Green Smart Campus Monitoring and Detection Using LoRa., , , and . Sensors, 21 (19): 6582 (2021)