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Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique.

, , , , and . CARLA, volume 697 of Communications in Computer and Information Science, page 131-145. (2016)

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The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Functional Verification of a RISC-V Vector Accelerator., , , , , , , , , and 2 other author(s). IEEE Des. Test, 40 (3): 36-44 (June 2023)Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory., , , , , , and . Comput. Sci. Eng., 18 (1): 80-87 (2016)Bluespec SystemVerilog., and . FPGAs for Software Programmers, Springer, (2016)HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA., , and . FCCM, page 163. IEEE Computer Society, (2015)SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core., and . SoC, page 1-4. IEEE, (2006)AxleDB: A novel programmable query processing platform on FPGA., , , , and . Microprocess. Microsystems, (2017)Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique., , , , and . CARLA, volume 697 of Communications in Computer and Information Science, page 131-145. (2016)Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology., , , , , , , , , and 38 other author(s). DCIS, page 1-6. IEEE, (2023)PAMS: Pattern Aware Memory System for embedded systems., , , , , , , and . ReConFig, page 1-7. IEEE, (2014)