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Automatic Selection of Process Corner Simulations for Faster Design Verification., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1312-1316 (2018)A novel gate grading approach for soft error tolerance in combinational circuits., , , and . CCECE, page 1-4. IEEE, (2016)A Compact Single-FPGA Fading-Channel Simulator., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (1): 84-88 (2008)A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy., , and . DATE, page 928-931. IEEE, (2019)Efficient allocation of packet-level forward error correction in video streaming over the Internet., , , and . J. Electronic Imaging, 16 (2): 023012 (2007)Design and evaluation of stochastic FIR filters., , , and . PACRIM, page 407-412. IEEE, (2015)Efficient architectures for 1-D and 2-D lifting-based wavelet transforms., , and . IEEE Trans. Signal Process., 52 (5): 1315-1326 (2004)Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM., , , , and . MTDT, page 117-122. IEEE Computer Society, (2002)An Investigation into Crosstalk Noise in DRAM Structures., , and . MTDT, page 123-. IEEE Computer Society, (2002)Stochastic circuit design and performance evaluation of vector quantization., , , and . ASAP, page 111-115. IEEE Computer Society, (2015)