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Adapting cache line size to application behavior., , , , and . International Conference on Supercomputing, page 145-154. ACM, (1999)Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor., , , , , , and . ICSAMOS, page 132-141. IEEE, (2008)Abstract Description of Pointer Data Structures: An Approach for Improving the Analysis and Optimization of Imperative Programs., , and . LOPLAS, 1 (3): 243-260 (1992)Performance Characterization of Itanium® 2-Based Montecito Processor., , , , , , and . SPEC Benchmark Workshop, volume 5419 of Lecture Notes in Computer Science, page 36-56. Springer, (2009)Author retrospective for a global resource-constrained parallelization technique., and . ICS 25th Anniversary, page 7-8. ACM, (2014)Cache-aware partitioning of multi-dimensional iteration spaces., , , , and . SYSTOR, page 15. ACM, (2009)A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms., , , , and . NPC, volume 8707 of Lecture Notes in Computer Science, page 459-470. Springer, (2014)Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-uniform Iteration Spaces., , and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 17-32. Springer, (2005)A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines., and . LCPC, volume 757 of Lecture Notes in Computer Science, page 49-63. Springer, (1992)Optimizing Program Performance via Similarity, Using a Feature-Agnostic Approach., , , and . APPT, volume 8299 of Lecture Notes in Computer Science, page 199-213. Springer, (2013)