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System level interconnect design for network-on-chip using interconnect IPs., , , and . SLIP, page 117-124. ACM, (2003)A Computational Scheme Based on Random Boolean Networks., , and . Trans. Computational Systems Biology, (2008)Can Dark Silicon Be Exploited to Prolong System Lifetime?, , , , , , and . IEEE Des. Test, 34 (2): 51-59 (2017)Private reliability environments for efficient fault-tolerance in CGRAs., , , , , and . Des. Autom. Embed. Syst., 18 (3-4): 295-327 (2014)InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V., , , , , , , , and . IEEE J. Solid State Circuits, 32 (9): 1371-1383 (1997)PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems., , , , and . Concurr. Comput. Pract. Exp., 27 (4): 1054-1067 (2015)A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process., and . VLSI, volume 162 of IFIP Conference Proceedings, page 23-34. Kluwer, (1999)Hardware/software partitioning and minimizing memory interface traffic., , , , and . EURO-DAC, page 226-231. IEEE Computer Society, (1994)Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation., , , , , and . PECCS, page 450-458. SciTePress, (2012)A DSL for the SegBus platform., , , and . SoCC, page 393-398. IEEE, (2009)