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Disambiguation of "Juan, Jorge"

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Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation.

, , , , and . IEEE Trans. Instrum. Meas., 60 (12): 3961-3963 (2011)

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Jorge Juan Robles

Hsiao-Mei Juan

Alexander Juan

Pere Juan i Tous

María Elena Juan Pardo

 

Other publications of authors with the same name

Long-term on-chip verification of systems with logical events scattered in time., , , , , and . Microprocess. Microsystems, 36 (5): 402-408 (2012)Design and implementation of a suitable core for on-chip long-term verification., , , , , and . SIES, page 234-237. IEEE, (2010)Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates., , , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 389-398. Springer, (2008)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells., , , , , , and . J. Low Power Electron., 7 (3): 444-452 (2011)Network Time Synchronization: A Full Hardware Approach., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 225-234. Springer, (2012)Design of a FFT/IFFT module as an IP core suitable for embedded systems., , , , , , , and . SIES, page 337-340. IEEE, (2007)Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation., , , , and . IEEE Trans. Instrum. Meas., 60 (12): 3961-3963 (2011)Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies., , , , , and . J. Low Power Electron., 6 (1): 93-102 (2010)Minimalistic SDHC-SPI hardware reader module for boot loader applications., , , , , and . Microelectron. J., (2017)