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Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications.

, , , and . J. Low Power Electron., 3 (2): 156-166 (2007)

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Hardware Coprocessor Synthesis from an ANSI C Specification., , , and . IEEE Des. Test Comput., 26 (4): 58-67 (2009)MCBCG: Model Checking Based Sequential Clock-Gating., and . HLDVT, page 20-25. IEEE Computer Society, (2009)Low Power Design with High-Level Power Estimation and Power-Aware Synthesis., , and . Springer, (2012)Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications., , , and . Power-aware Computing Systems, volume 07041 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2007)VT Matrix Multiply Design for MEMOCODE '07., , , , and . MEMOCODE, page 95-96. IEEE Computer Society, (2007)Coprocessor design space exploration using high level synthesis., , and . ISQED, page 879-884. IEEE, (2010)Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications., , , and . J. Low Power Electron., 3 (2): 156-166 (2007)The Model Checking View to Clock Gating and Operand Isolation., , , and . ACSD, page 181-190. IEEE Computer Society, (2010)High Level Power Estimation Models for FPGAs., , and . ISVLSI, page 7-12. IEEE Computer Society, (2011)