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Cost Modeling and Projection for Stacked Nanowire Fabric., and . CoRR, (2017)A New Concept for Computing Using Interconnect Crosstalks., , , , , and . ICRC, page 1-2. IEEE, (2017)A Novel Analog to Digital Conversion Concept with Crosstalk Computing., , , , and . NANOARCH, page 121-123. ACM, (2018)A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks., , , , and . ICRC, page 1-6. IEEE, (2018)A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs., , , and . CoRR, (2019)On circuit developments to enable large scale circuit design while computing with noise., , , and . Integr., (2022)Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits., , , , , and . NANOARCH, page 114-120. ACM, (2018)Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric., , and . NANOARCH, page 155-161. IEEE, (2017)Fine-grained 3-D CMOS concept using stacked horizontal nanowire., , and . NANOARCH, page 151-152. ACM, (2016)Crosstalk Noise based Configurable Computing: A New Paradigm for Digital Electronics., , , , and . CoRR, (2020)