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Disambiguation of "U., Seng-Pan"

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A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique.

, , and . APCCAS, page 183-186. IEEE, (2006)

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Peter Seng

Stefan Seng

Katja Seng

Helmut Seng

Gerhard Seng

 

Other publications of authors with the same name

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (2): 489-501 (2019)Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (6): 1819-1829 (2018)A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration., , , , and . IEEE J. Solid State Circuits, 53 (3): 850-860 (2018)60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration., , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2576-2588 (2017)An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC., , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)A digital LDO with transient enhancement and limit cycle oscillation reduction., , , and . APCCAS, page 25-28. IEEE, (2016)20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control., , , and . ISSCC, page 342-343. IEEE, (2017)A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC., , , , and . IEEE J. Solid State Circuits, 51 (2): 365-377 (2016)A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS., , and . IEEE J. Solid State Circuits, 39 (1): 87-99 (2004)Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems., , and . ISCAS (4), page 441-444. IEEE, (2002)