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Disambiguation of "Kim, Tony Tae-Hyoung"

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An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of VMIN Degradation.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (3): 584-593 (2012)

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Hyoung-Gook Kim

Moo-Hyoung Kim

Hyoung Seok Kim

Hyoung-Soo Kim

Tae-hy Kim

 

Other publications of authors with the same name

Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement., and . ISOCC, page 163-166. IEEE, (2011)On-chip reliability monitors for measuring circuit degradation., , , and . Microelectron. Reliab., 50 (8): 1039-1053 (2010)A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 340-352 (January 2023)An Area Efficient 1024-Point Low Power Radix-22 FFT Processor With Feed-Forward Multiple Delay Commutators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3291-3299 (2018)A Self-Adaptive Time-Based MPPT With 96.2% Tracking Efficiency and a Wide Tracking Range of 10 µA to 1 mA for IoT Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2334-2345 (2017)SRAM Array Structures for Energy Efficiency Enhancement., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (6): 351-355 (2013)NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (9): 602-606 (2013)A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing., , , and . IEEE J. Solid State Circuits, 43 (2): 518-529 (2008)A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance., , and . Microelectron. J., (2017)A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications., , , and . IEEE Open J. Circuits Syst., (2021)