Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Automated Design For Yield Through Defect Tolerance., , and . VTS, page 1-6. IEEE, (2020)Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (11): 3155-3164 (2014)FireBird: PowerPC e200 based SoC for high temperature operation., , , , , , , and . CICC, page 1-4. IEEE, (2013)Synthesis strategies for sub-VT systems., , , , and . ECCTD, page 552-555. IEEE, (2011)An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing., , , , , , and . VLSI-SoC (Selected Papers), volume 418 of IFIP Advances in Information and Communication Technology, page 88-106. Springer, (2012)Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop., , , , , , and . ISCAS, page 1-4. IEEE, (2017)Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 358-362 (2016)Two-port low-power gain-cell storage array: Voltage scaling and retention time., , and . ISCAS, page 2469-2472. IEEE, (2012)Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems., , , and . ACM Great Lakes Symposium on VLSI, page 343-346. ACM, (2011)Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 173-182 (2011)