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On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs., , , and . LATW, page 1-4. IEEE, (2014)Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor., , , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 175-184. Springer, (2012)Methodology for Application-Dependent Degradation Analysis of Memory Timing., , , , , , and . DATE, page 162-167. IEEE, (2019)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes., , , , , , , , , and 5 other author(s). Microprocess. Microsystems, 39 (8): 1039-1051 (2015)Comphy - A compact-physics framework for unified modeling of BTI., , , , , , , , , and 4 other author(s). Microelectron. Reliab., (2018)Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 601-610 (2019)Experimental evidences and simulations of trap generation along a percolation path., , , , , , , , , and . ESSDERC, page 226-229. IEEE, (2015)Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level., , , , , , , , , and 5 other author(s). DATE, page 1-10. IEEE, (2023)Design enablement of CFET devices for sub-2nm CMOS nodes., , , , , , , and . DATE, page 29-33. IEEE, (2022)Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)