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Strong and Efficient Cache Side-Channel Protection using Hardware Transactional Memory.

, , , , , and . USENIX Security Symposium, page 217-233. USENIX Association, (2017)

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Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches., , and . USENIX Security Symposium, page 897-912. USENIX Association, (2015)NetSpectre: Read Arbitrary Memory over Network., , , , and . ESORICS (1), volume 11735 of Lecture Notes in Computer Science, page 279-299. Springer, (2019)How Trusted Execution Environments Fuel Research on Microarchitectural Attacks., and . IEEE Secur. Priv., 18 (5): 18-27 (2020)Systematic Analysis of Programming Languages and Their Execution Environments for Spectre Attacks., , , , , , , and . CoRR, (2021)Software-basierte Mikroarchitekturangriffe.. Ausgezeichnete Informatikdissertationen, volume D-18 of LNI, GI, (2017)RAMBleed: Reading Bits in Memory Without Accessing Them., , , and . SP, page 695-711. IEEE, (2020)Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks., , , , , , and . SP, page 2273-2287. IEEE, (2023)The Evolution of Transient-Execution Attacks., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2020)Nethammer: Inducing Rowhammer Faults through Network Requests., , , , , , and . EuroS&P Workshops, page 710-719. IEEE, (2020)PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks., , , , , and . DSN, page 95-108. IEEE, (2023)