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Synthesis of hazard-free asynchronous circuits with bounded wire delays.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (1): 61-86 (1995)

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Solving the State Assignment Problem for Signal Transition Graphs., , , and . DAC, page 568-572. IEEE Computer Society Press, (1992)Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool., , , and . DAC, page 254-260. ACM Press, (1995)Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis., , , and . IEEE Access, (2017)A software development tool chain for a reconfigurable processor., , and . CASES, page 93-98. ACM, (2001)Enabling adaptability through elastic clocks., , and . DAC, page 8-10. ACM, (2009)A Fully-Automated Desynchronization Flow for Synchronous Circuits., , , and . DAC, page 982-985. IEEE, (2007)Guest Editors' Introduction: Trends and Directions in Microelectronics., and . IEEE Micro, 23 (3): 6-7 (2003)A Framework for Modeling, Simulation and Automatic Code Generation of Sensor Network Application., , , , and . SECON, page 515-522. IEEE, (2008)Incremental high-level synthesis., , , , , , and . ASP-DAC, page 701-706. IEEE, (2010)Wireless Sensor Networks., and . Handbook of Hardware/Software Codesign, (2017)