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A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems.

, , , , and . IEEE Trans. Computers, 66 (2): 212-225 (2017)

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Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield., , and . ISQED, page 41-48. IEEE, (2012)Pain-mitigation Techniques for Model-based Engineering using Domain-specific Languages., , , , and . MODELSWARD, page 752-764. SciTePress, (2018)Run-time power-down strategies for real-time SDRAM memory controllers., , and . DAC, page 988-993. ACM, (2012)Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs., , and . ACM Trans. Embed. Comput. Syst., 13 (2s): 61:1-61:24 (2014)Dynamic Command Scheduling for Real-Time Memory Controllers., , and . ECRTS, page 3-14. IEEE Computer Society, (2014)Architectures and modeling of predictable memory controllers for improved system integration., and . DATE, page 851-856. IEEE, (2011)Improved Power Modeling of DDR SDRAMs., , and . DSD, page 99-108. IEEE Computer Society, (2011)Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs., , and . PDP, page 701-710. IEEE Computer Society, (2015)Conservative open-page policy for mixed time-criticality memory controllers., , and . DATE, page 525-530. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache., , , , and . ECRTS, volume 76 of LIPIcs, page 18:1-18:21. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2017)