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Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 460-463 (2000)

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Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations., and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 127-136. Springer, (2006)Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 360-369. Springer, (2006)Computing at the ultimate low-energy limits.. SBCCI, page 1. ACM, (2010)An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.. IEEE Trans. Very Large Scale Integr. Syst., 2 (1): 124-128 (1994)Dual-edge triggered storage elements and clocking strategy for low-power systems., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (5): 577-590 (2005)Clocking and clocked storage elements in a multi-gigahertz environment.. IBM J. Res. Dev., 47 (5-6): 567-584 (2003)Introduction., and . VLSI Signal Processing, 3 (4): 263 (1991)Dynamic Flip-Flop with Improved Power., and . ICCD, page 323-326. IEEE Computer Society, (2000)Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders., , , , and . IEEE Symposium on Computer Arithmetic, page 272-279. IEEE Computer Society, (2003)Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders., , and . ARITH, page 10-17. IEEE, (2015)