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An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4999-5010 (2020)

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Low power design for SoC with power management unit., , , , and . ASICON, page 719-722. IEEE, (2011)A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control., , , , and . ASICON, page 870-873. IEEE, (2011)A Data Prefetch and Reuse Strategy for Coarse-Grained Reconfigurable Architectures., , , , and . IEICE Trans. Inf. Syst., 96-D (3): 616-623 (2013)An Analytical Model for Domain-Specific Accelerator Deploying Sparse LU Factorization., , and . ASICON, page 1-4. IEEE, (2023)14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS., , , , , , , , and . ISSCC, page 230-232. IEEE, (2020)Domain Strategy and Coverage Metric for Validation., , , , and . ISQED, page 40-45. IEEE Computer Society, (2005)A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects., , , , , and . DATE, page 1-6. IEEE, (2024)A Statistical Timing Model for Low Voltage Design Considering Process Variation., , , , , and . ICCAD, page 1-8. ACM, (2019)RNA: Reconfigurable LSTM Accelerator with Near Data Approximate Processing., , , and . FPT, page 311-314. IEEE, (2019)An artificial neural network model of LRU-cache misses on out-of-order embedded processors., , , and . Microprocess. Microsystems, (2017)