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Disambiguation of "Garrido, Mario"

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The Serial Commutator FFT.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 974-978 (2016)

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Jose Garrido

Myriam Garrido

Blas Garrido

Simone Marion

Ernst Marioth-Wirtz

 

Other publications of authors with the same name

A 1 Million-Point FFT on a Single FPGA., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3863-3873 (2019)Optimum Circuits for Bit-Dimension Permutations., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1148-1160 (2019)A Serial Commutator Fast Fourier Architecture for Real-Valued Signals., , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1693-1697 (2018)Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal.. IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 657-661 (2019)Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G., and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (10): 4004-4014 (October 2023)Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices., and . J. Signal Process. Syst., 95 (4): 543-550 (April 2023)Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations., , and . J. Signal Process. Syst., 90 (11): 1581-1582 (2018)Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (10): 2869-2877 (2014)An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and Beyond., and . DCIS, page 1-6. IEEE, (2023)Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued Serial FFT., , and . ISCAS, page 1-5. IEEE, (2019)