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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

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19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. ISSCC, page 324-325. IEEE, (2016)A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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Disambiguation of "Iyer, Amrutha"

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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Please choose a person to relate this publication to

Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Iyer, Amrutha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Please choose a person to relate this publication to

Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.