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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

, , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC., , , , , , and . ESSCIRC, page 193-196. IEEE, (2012)A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling., , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation., , and . CICC, page 121-124. IEEE, (2009)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial., and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (12): 881-885 (2009)Open-Loop Wide-Bandwidth Phase Modulation Techniques., , and . J. Electr. Comput. Eng., (2011)19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC., , , , , , , and . ISSCC, page 324-325. IEEE, (2016)Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (6): 1221-1230 (2010)A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation., and . IEEE J. Solid State Circuits, 46 (3): 615-626 (2011)A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation., , and . IEEE J. Solid State Circuits, 45 (8): 1522-1532 (2010)