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Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation., , and . ISCAS, page 2225-2228. IEEE, (2009)An efficient pulse flip-flop based launch-on-shift scan cell., and . ISCAS, page 4105-4108. IEEE, (2010)A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes., , , , , and . ICASSP (3), page 972-975. IEEE, (2006)Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG., and . GENSiPS, page 87-90. IEEE, (2011)A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic., and . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 326-331 (2008)Fast, Ring-Based Design of 3-D Stacked DRAM., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1731-1741 (2019)Boolean satisfiability on a graphics processor., and . ACM Great Lakes Symposium on VLSI, page 123-126. ACM, (2010)An ASIC design methodology with predictably low leakage, using leakage-immune standard cells., and . ISLPED, page 128-133. ACM, (2003)A design approach for radiation-hard digital electronics., , , and . DAC, page 773-778. ACM, (2006)A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (6): 1225-1238 (2011)