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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

, , , , , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)

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Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models., , , and . SIGMAP, page 47-54. INSTICC Press, (2008)A Low Power 256 KB SRAM Design., , , , and . VLSI Design, page 67-71. IEEE Computer Society, (1999)Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling., and . VLSI Design, page 821-826. IEEE Computer Society, (2004)Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Digital fractional-order differentiator and integrator models based on first-order and higher order operators., , and . I. J. Circuit Theory and Applications, 39 (5): 461-474 (2011)A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer., and . VLSI Design, page 484-487. IEEE Computer Society, (2000)Micropipeline Architecture for Multiplier-less FIR Filters., , , and . VLSI Design, page 451-456. IEEE Computer Society, (1997)A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip., , , and . VLSI Design, page 828-831. IEEE Computer Society, (2005)Battery aware dynamic scheduling for periodic task graphs., , , , and . IPDPS, IEEE, (2006)Impact of crosstalk and process variation on capture power reduction for at-speed test., , and . VTS, page 1-6. IEEE Computer Society, (2016)