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System level interconnect design for network-on-chip using interconnect IPs., , , and . SLIP, page 117-124. ACM, (2003)A Computational Scheme Based on Random Boolean Networks., , and . Trans. Computational Systems Biology, (2008)Hardware/software partitioning and minimizing memory interface traffic., , , , and . EURO-DAC, page 226-231. IEEE Computer Society, (1994)A DSL for the SegBus platform., , , and . SoCC, page 393-398. IEEE, (2009)Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems., , , , and . PECCS, page 573-581. SciTePress, (2011)Combinatorial architectural level power optimization for a class of orthogonal transforms., and . ISCAS (1), page 70-75. IEEE, (1999)Efficient congestion-aware selection method for on-chip networks., , , , and . ReCoSoC, page 1-4. IEEE, (2011)Smart energy efficient gateway for Internet of mobile things., , , , , , , , and . CCNC, page 1016-1017. IEEE, (2017)Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip., , and . DSD, page 551-555. IEEE Computer Society, (2007)Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid., , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 766-770 (2008)