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Architecture and synthesis for multi-cycle on-chip communication., , , , and . CODES+ISSS, page 77-78. ACM, (2003)GraphZoom: A multi-level spectral approach for accurate and scalable graph embedding., , , , and . CoRR, (2019)GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding., , , , and . ICLR, OpenReview.net, (2020)Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (11): 1817-1830 (2017)Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel., , , , and . CoRR, (2024)Special Session: Machine Learning for Embedded System Design., , , , , , , , , and 1 other author(s). CODES+ISSS, page 28-37. IEEE, (2023)A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs., , , , , , , and . FPGA, page 185. ACM, (2024)Formal Verification of Source-to-Source Transformations for HLS., , , , , , and . FPGA, page 97-107. ACM, (2024)Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks., , , , , and . ASP-DAC, page 152-157. ACM, (2021)High-level synthesis with timing-sensitive information flow enforcement., , , and . ICCAD, page 88. ACM, (2018)