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Disambiguation of "Cotofana, Sorin"

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Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.

, , , , and . Map2MPSoC/SCOPES, page 13-21. ACM, (2012)

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Sebastian Cotofana

Julia Sorina-Müller

Kai Söring

Julia Sorina-Müller

Jürgen Söring

 

Other publications of authors with the same name

The MOLEN rho-mu-Coded Processor., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 275-285. Springer, (2001)Periodic symmetric functions, serial addition, and multiplication with neural networks., and . IEEE Trans. Neural Networks, 9 (6): 1118-1128 (1998)Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 899-906. Springer, (2004)A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study., , , , and . Embedded Processor Design Challenges, volume 2268 of Lecture Notes in Computer Science, page 224-241. Springer, (2002)A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst., 67-I (12): 4247-4258 (2020)Field-Programmable Custom Computing Machines - A Taxonomy -., , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 79-88. Springer, (2002)Spin Wave Threshold Logic Gates., , , , , and . NANOARCH, page 31:1-31:6. ACM, (2023)Spin Wave Based Full Adder., , , , , and . ISCAS, page 1-5. IEEE, (2021)2-Output Spin Wave Programmable Logic Gate., , , , , and . ISVLSI, page 60-65. IEEE, (2020)Can SG-FET Replace FET in Sleep Mode Circuits?, , , , and . NanoNet, volume 20 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 99-104. Springer, (2009)