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Disambiguation of "Koyanagi, Yoichi"

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Synfinity II-a high-speed interconnect with 2 GBytes/sec self-configurable physical link.

, , , and . Hot Interconnects, page 23-29. IEEE Computer Society, (2001)

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Yoichi Kiuchi

Yoichi Otani

Yoichi Ishikawa

 

Other publications of authors with the same name

Fault-Tolerant Design of Neural Networks for Solving Optimization Problems., and . IEEE Trans. Computers, 45 (12): 1450-1455 (1996)Fault Tolerant Neural Networks in Optimization Problems., and . FTCS, page 412-418. IEEE Computer Society, (1992)Design of Neural Networks to Tolerate the Mixture of Two Types of Faults., and . FTCS, page 268-277. IEEE Computer Society, (1993)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (12): 3258-3267 (2013)A 10th generation 16-core SPARC64 processor for mission-critical UNIX server., , , , , , , , , and 4 other author(s). ISSCC, page 60-61. IEEE, (2013)The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 49 (1): 32-40 (2014)