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Disambiguation of "Yasufuku, Tadashi"

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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.

, , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 918-921 (2012)

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Tadashi Obara

Tadashi Otsuru

Tadashi Makabe

Tadashi Kito

Tadashi Yamagata

 

Other publications of authors with the same name

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates., , , , , , and . DAC, page 984-989. ACM, (2011)Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories., , , , , , and . 3DIC, page 1-4. IEEE, (2009)Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 1175-1179 (2013)Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories., , , , , , and . IEICE Trans. Electron., 93-C (3): 317-323 (2010)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection., , , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 249-259 (2010)A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS., , , , , , , , , and . ISSCC, page 472-473. IEEE, (2009)12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics., , , , , , and . ISLPED, page 163-168. IEEE/ACM, (2011)Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS., , , , , , and . ISLPED, page 21-26. IEEE/ACM, (2011)A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology., , , , , , , , , and 54 other author(s). ISSCC, page 336-338. IEEE, (2018)