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Modelling and Verification of Timing Conditions with the Boyer Moore Prover., and . TPCD, volume A-10 of IFIP Transactions, page 111-127. North-Holland, (1992)Correct interactive transformational synthesis of DSP hardware., , and . EURO-DAC, page 16-21. EEE Computer Society, (1991)Design and security evaluation of balanced 1-of-n circuits., , , and . IET Comput. Digit. Tech., 6 (2): 125-135 (2012)WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets., , and . Real Time Syst., 18 (2/3): 275-288 (2000)Modelling, analysis and synthesis of asynchronous control circuits using Petri nets., , , and . Integr., 21 (3): 143-170 (1996)Modelling and verification of an atomic action protocol implemented in Ada., , , , , , and . Comput. Syst. Sci. Eng., 16 (3): 173-182 (2001)Analysing Superscalar Processor Architectures with Coloured Petri Nets., , and . Int. J. Softw. Tools Technol. Transf., 2 (2): 182-191 (1998)Asynchronous microprocessors: From high level model to FPGA implementation., , , and . J. Syst. Archit., 45 (12-13): 975-1000 (1999)High-Level Modeling and Design of Asynchronous Interface Logic., , and . IEEE Des. Test Comput., 12 (1): 32-40 (1995)Dynamic global security-aware synthesis using SystemC., , , , and . IET Comput. Digit. Tech., 1 (4): 405-413 (2007)