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Disambiguation of "Burg, Andreas"

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A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing.

, , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 329-340 (2018)

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Andreas Burg

Andreas Marzell Burg

Josef Burg

Richard Burg

Arnold Burg

 

Other publications of authors with the same name

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs, , , , , , , , , and . ACM Trans. Embedded Comput. Syst., 14 (2): 33:1--33:23 (2015)Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms., , , , , and . DATE, page 396-399. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation., , , and . ISCAS, page 3530-3533. IEEE, (2007)A signal processor for Gaussian message passing., , , , , and . ISCAS, page 1969-1972. IEEE, (2014)Spatial Multiplexing of QPSK Signals with a Single Radio: Antenna Design and Over-the-Air Experiments., , , , and . CoRR, (2016)PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes., , , , , , , and . CoRR, (2017)A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI., , , and . ISCAS, page 1-4. IEEE, (2018)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space., , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1207-1217 (2020)Digital predistortion of hardware impairments for full-duplex transceivers., , and . GlobalSIP, page 878-882. IEEE, (2017)