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Constrained least squares detector for OFDM/SDMA-based wireless networks.

, , , , and . IEEE Trans. Wirel. Commun., 2 (1): 129-140 (2003)

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Performance Through Hierarchy in Static Timing Verification., , and . IFIP Congress (1), volume A-12 of IFIP Transactions, page 703-709. North-Holland, (1992)A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging., , , , and . VLSI Design, page 48-. IEEE Computer Society, (2001)Memory organization for video algorithms on programmable signal processors., , and . ICCD, page 552-557. IEEE Computer Society, (1995)Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs., , , and . VLSI Signal Processing, 18 (1): 39-50 (1998)Nonlinear transformations for high level regular array ASIC synthesis., , and . VLSI Signal Processing, 4 (4): 259-268 (1992)Static Timing Analysis of Dynamically Sensitizable Paths., , and . DAC, page 568-573. ACM Press, (1989)Loop Optimization in Register-Transfer Scheduling for DSP-Systems., , and . DAC, page 826-831. ACM Press, (1989)Solving large scale assignment problems in high-level synthesis by approximative quadratic programming., , , and . ACM Great Lakes Symposium on VLSI, page 19-24. ACM, (2001)An intelligent module generator environment., , , and . DAC, page 730-735. IEEE Computer Society Press, (1986)