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Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors.

, , , and . IEEE Trans. Computers, 62 (5): 914-928 (2013)

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The design and implementation of a low-latency on-chip network., , and . ASP-DAC, page 164-169. IEEE, (2006)CHERI: A Hardware-Software System to Support the Principle of Least Privilege., , and . ERCIM News, (2016)An Energy and Performance Exploration of Network-on-Chip Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (3): 319-329 (2009)How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel., , and . ACM Queue, 21 (3): 54-64 (2023)Position Paper: Defending Direct Memory Access with CHERI Capabilities., , , , , and . HASP@MICRO, page 7:1-7:9. ACM, (2020)CheriRTOS: A Capability Model for Embedded Devices., , , , , , , , , and 6 other author(s). ICCD, page 92-99. IEEE Computer Society, (2018)JMA: The Java-Multithreading Architecture for Embedded Processors., and . ICCD, page 527-. IEEE Computer Society, (2002)A Network of Time-Division Multiplexed Wiring for FPGAs., , and . NOCS, page 35-44. IEEE Computer Society, (2008)Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation., , , , and . FCCM, page 133-140. IEEE Computer Society, (2012)Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals., , , , , , and . NDSS, The Internet Society, (2019)