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A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1480-1484 (2018)

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High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering., , and . ISCAS (1), page 204-207. IEEE, (2001)A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy., , and . ISCAS, IEEE, (2006)A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications., , , and . ISCAS, IEEE, (2006)An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver., , , , , , , and . ISCAS (1), page 1068-1071. IEEE, (2004)A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA., , and . ISCAS (4), page 3099-3102. IEEE, (2005)A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs., , , , , and . ISCAS, page 4061-4064. IEEE, (2010)A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators., , and . ISCAS (4), page 3095-3098. IEEE, (2005)Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs., , , , , and . VLSI Design, (2010)Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects., , and . IEEE Trans. Instrumentation and Measurement, 53 (4): 1279-1288 (2004)A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller., , and . APCCAS, page 396-399. IEEE, (2008)