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A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC., , , , , , and . ISCAS, page 1117-1120. IEEE, (2011)10b 150MS/s 0.4mm2 45nm CMOS ADC based on process-insensitive amplifiers., , , , , and . ISCAS, page 316-. IEEE, (2013)A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer., , , , , , , , and . ICECS, page 637-640. IEEE, (2012)A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique., and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 274-278 (2011)A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC., , , , , , , , and . IEEE J. Solid State Circuits, 43 (5): 1195-1206 (2008)A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators., , , , and . IEEE J. Solid State Circuits, 53 (10): 2772-2782 (2018)A 12-b, 10-MHz, 250-mW CMOS A/D converter., , , , and . IEEE J. Solid State Circuits, 31 (12): 2030-2035 (1996)A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications., , , , , , and . IEEE J. Solid State Circuits, 56 (4): 1197-1206 (2021)A CMOS Analog Front-End for Hall Sensor Readout IC., , , and . ICEIC, page 1-3. IEEE, (2024)An improved algorithmic ADC clocking scheme., , and . ISCAS (1), page 589-592. IEEE, (2004)